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march 2002 copyright ? alliance semiconductor. all rights reserved. ? as7c4098 as7c34098 5v/3.3v 256k 16 cmos sram 5/23/02; v.1.8 alliance semiconductor p. 1 of 12 features ? as7c4098 (5v version) as7c34098 (3.3v version) industrial and commercial temperature organization: 262,144 words 16 bits center power and ground pins high speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time low power consumption: active - 1375 mw (as7c4098)/max @ 12 ns - 468 mw (as7c34098)/max @ 12 ns low power consumption: standby - 110 mw (as7c4098)/max cmos - 72 mw (as7c34098)/max cmos individual byte read/write controls easy memory expansion with ce , oe inputs ttl- and cmos-compatible, three-state i/o 44-pin jedec standard packages - 400-mil soj -tsop 2 - 48-ball fbga 7 x 11 mm esd protection 2000 volts latch-up current 200 ma logic block diagram 1024 256 16 array (4,194,304) oe ce we column decoder row decoder a0 a1 a2 a3 a4 a6 a7 a8 v cc gnd a12 a5 a9 a10 a11 a14 a15 a16 a17 a13 control circuit i/o1?i/o8 i/o9?i/o16 ub lb i/o buffer pin arrangement for soj and tsop 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o14 i/o13 gnd v cc i/o12 i/o11 i/o10 i/o9 nc a14 a13 a12 a11 a10 a4 ce i/o1 i/o2 i/o3 i/o4 v cc gnd i/o5 i/o6 i/o7 i/o8 we a5 a6 a7 tsop2 21 22 a8 a9 ub lb i/o16 i/o15 2 a1 3 a2 4 a3 1 a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a16 a15 oe a17 44-pin (400 mil) soj selection guide ?10 ?12 ?15 ?20 unit maximum address access time 10 12 15 20 ns maximum output enable access time 5 6 7 9 ns maximum operating current as7c4098 ? 250 220 180 ma as7c34098 160 130 110 100 ma maximum cmos standby current as7c4098 ? 20 20 20 ma as7c34098 20 20 20 20 ma
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 2 of 12 48-bga ball-grid-array package 1 2 3 4 5 6 alb oe a0 a1 a2 nc bi/o9 ub a3 a4 ce i/o1 c i/o10 i/o11 a5 a6 i/o2 i/o3 dv ss i/o12 a17 a7 i/o4 v cc ev cc i/o13 nc a16 i/o5 v ss f i/o15 i/o14 a14 a15 i/o6 i/o7 g i/o16 nc a12 a13 we i/o8 h nc a8 a9 a10 a11 nc 48-bga ball-grid-array package - version 2 alternative 1 2 3 4 5 6 alb oe a0 a1 a2 nc bi/o1 ub a3 a4 ce i/o9 c i/o2 i/o3 a5 a6 i/o11 i/o10 dv ss i/o4 a17 a7 i/o12 v cc ev cc i/o5 nc a16 i/o13 v ss f i/o7 i/o6 a14 a15 i/o14 i/o15 g i/o8 nc a12 a13 we i/o16 h nc a8 a9 a10 a11 nc ball arrangement bga
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 3 of 12 functional description the as7c4098 and as7c34098 are high-performance cmos 4,1 94,304-bit static random access memory (sram) devices organized as 262,144 words 16 bits. they are designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 5/6/7/8 ns are ideal for high-performance applications. the chip enable input ce permits easy memory expansion with multiple-bank memory systems. when ce is high the device enters standby mode. the standard as7c4098 is guaranteed not to exceed 110 mw power consumption in cmos standby mode. a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o1?i/o16 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after ou tputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input addr ess. when either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. these devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. lb controls the lower bits, i/o1?i/o8, and ub controls the higher bits, i/o9?i/o16. all chip inputs and outputs are ttl- and cmos-compatible, and operation is from either a single 5v (as7c4098) or 3.3v (as7c34098) supply. both devices are available in the jedec standard 400-ml, 44-pin soj, tsop 2, and 48 - csp/bga packages. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. th is is a stress rating only and functional operation of the device at these or any other conditions outsid e those indicated in the operation al sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings parameter device symbol min max unit vo l t ag e o n v cc relative to gnd as7c4098 v t1 ?0.50 +7.0 v as7c34098 v t1 ?0.50 +5.0 v voltage on any pin relative to gnd v t2 ?0.50 v cc +0.50 v power dissipation p d ?1.5w storage temperature (plastic) t stg ?65 +150 c ambient temperature with v cc applied t bias ?55 +125 c dc current into outputs (low) i out ?20ma truth table ce we oe lb ub i/o1?i/o8 i/o9?i/o16 mode hxxxx high z high zstandby (i sb , i sb1 ) lhhxx high z high z output disable (i cc ) lxxhh lhl lh d out high z read (i cc ) hl high z d out ll d out d out llx lh d in high z write (i cc ) hl high z d in ll d in d in key: x = don?t care, l = low, h = high.
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 4 of 12 recommended operating conditions parameter symbol min ty p i c a l max unit supply voltage as7c4098 v cc (12/15/20) 4.5 5.0 5.5 v as7c34098 v cc (10) 3.15 3.3 3.6 v as7c34098 v cc (12/15/20) 3.0 3.3 3.6 v input voltage as7c4098 v ih 2.2 ? v cc + 0.5 v as7c34098 v ih 2.0 ? v cc + 0.5 v v il ?0.5 1 1 v il min = ?3.0v for pulse width less than t rc /2. ?0.8v ambient operating temperature commercial t a 0? 70 c industrial t a ?40 ? 85 c dc operating characteristics (over the operating range) parameter symbol test conditions ?10 ?12 ?15 ?20 unit min max min max min max min max input leakage current |i li | v cc = max v in = gnd to v cc ?1?1?1?1a output leakage current |i lo | v cc = max ce = v ih or oe = v ih or we = v il v i/o = gnd to v cc ?1?1?1?1a operating power supply current i cc v cc = max min cycle, 100% duty ce = v il , i out = 0ma as7c4098 ? ? ? 250 ? 220 ? 180 ma as7c34098 ? 160 ? 130 ? 110 ? 100 ma standby power supply current i sb v cc = max ce = v ih , f = max as7c4098 ? ? ? 60 ? 60 ? 60 ma as7c34098 ? 60 ? 60 ? 60 ? 60 ma i sb1 v cc = max ce v cc ? 0.2v, v in v cc ? 0.2v or v in 0.2v, f = 0 as7c4098 ? ? ? 20 ? 20 ? 20 ma as7c34098 ? 20 ? 20 ? 20 ? 20 ma output voltage v ol i ol = 8 ma, v cc = min ? 0.4 ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 ? 2.4 ? 2.4 ? 2.4 ? v capacitance (f = 1mhz, t a = 25 c, v cc = nominal) parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe , ub , lb v in = 0v 6 pf i/o capacitance c i/o i/o v in = v out = 0v 8 pf
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 5 of 12 key to switching waveforms read waveform 1 (address controlled) read cycle (over the operating range) parameter symbol ?10 ?12 ?15 ?20 unit notes min max min max min max min max read cycle time t rc 10 ? 12?15?20? ns address access time t aa ? 10 ? 12 ? 15 ? 20 ns chip enable (ce ) access time t ace ? 10 ? 12 ? 15 ? 20 ns output enable (oe ) access time t oe ? 5 ?6?7?8ns output hold from address change t oh 3 ? 3?3?3?ns5 ce low to output in low z t clz 0 ? 3?0?0?ns4, 5 ce high to output in higfch z t chz ? 5 ?6?7?9ns4, 5 oe low to output in low z t olz 0 ? 0?0?0?ns4, 5 oe high to output in high z t ohz ? 5 ?6?7?9ns4, 5 lb , ub access time t ba ? 5 ?6?7?8ns lb , ub low to output in low z t blz 0 ? 0?0?0?ns lb , ub high to output in high z t bhz ? 5 ?6?7?9ns power up time t pu 0 ? 0?0?0?ns5 power down time t pd ? 10 ? 12 ? 15 ? 20 ns 5 undefined/don?t care falling input rising input t oh t aa t rc t oh data out address data valid previous data valid
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 6 of 12 read waveform 2 (ce , oe , ub , lb controlled) write cycle (over the operating range) parameter symbol ?10 ?12 ?15 ?20 unit note min max min max min max min max write cycle time t wc 10 ? 12 ? 15 ? 20 ? ns chip enable (ce ) to write end t cw 7?8?10?12?ns address setup to write end t aw 7?8?10?12?ns address setup time t as 0?0?0?0?ns write pulse width (oe = high) t wp1 7?8?10?12?ns write pulse width (oe = low) t wp2 10 ? 12 ? 15 ? 20 ? ns write recovery time t wr 0?0?0?0?ns address hold from end of write t ah 0?0?0?0?ns data valid to write end t dw 5?6 7?9?ns data hold time t dh 0 ? 0 ? 0 ? 0 ? ns 4, 5 write enable to output in high-z t wz 05060709ns4, 5 output active from write end t ow 3 ? 3 ? 3 ? 3 ? ns 4, 5 byte enable low to write end t bw 7 ? 8 ? 10 ? 12 ? ns 4, 5 data valid t rc t aa t blz t ba t oe t olz t oh t ohz t chz t bhz t ace t lz address oe ce lb , ub data out
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 7 of 12 write waveform 1(we controlled) write waveform 2 (ce controlled) address ce lb , ub we data in data out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t ah data undefined high z data valid t wr address ce lb , ub we data in t wc t cw t bw t wp t dw t dh t ow t wz t ah data out data undefined high z high z t as t aw data valid t clz t wr
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 8 of 12 write waveform 3 ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, c. 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the la st valid address to the first transitioning address. 10 ce or we must be high during addr ess transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the la st valid address to the first transitioning address. 12 not applicable. 13 c = 30pf, except on high z an d low z parameters, where c = 5pf. address ce lb , ub we data in t wc t cw t bw t wp t dw t dh t wz t ah data out data undefined high z high z t as t aw data valid t wr - output load: see figure b or figure c. - input pulse level: gnd to 3.0v. see figure a. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 10% 90% 10% 90% gnd +3.0v 2 ns figure a: input pulse 255 ? c(14) 480 ? d out gnd +5v figure b: 5v output load 350 ? c(14) 320 ? d out gnd +3.3v figure c: 3.3v output load 168 ? thevenin equivalent: d out +1.728v (5v and 3.3v)
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 9 of 12 typical dc and ac characteristics
supply voltage (v) min max nominal 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current icc, isb ambient temperature ( c) ?55 80 125 35 ?10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage vcc i cc i sb i cc i sb ambient temperature ( c) ?55 80 125 35 ?10 0.2 1 0.04 5 25 625 normalized isb1 (log scale) normalized supply current i sb1 vs. ambient temperature t a v cc = v cc (nominal) supply voltage (v) min max nominal 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature ( c) ?55 80 125 35 ?10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 075 100 50 25 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc v cc = v cc (nominal) t a = 25 c v cc = v cc (nominal) t a = 25 c output voltage (v) v cc 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) v cc output sink current (ma) output sink current i ol vs. output voltage v ol vs. output voltage v oh 0 20 60 80 40 100 120 140 v cc = v cc (nominal)pl t a = 25 c v cc = v cc (nominal) t a = 25 c capacitance (pf) 0 750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change ? t aa vs. output capacitive loading v cc = v cc (nominal) 00
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 10 of 12 package dimensions 44-pin tsop 2 min (mm) max (mm) a 1.2 a 1 0.05 a 2 0.95 1.05 b 0.25 0.45 c 0.15 (typical) d 18.28 18.54 e 10.06 10.26 h e 11.56 11.96 e 0.80 (typical) l 0.40 0.60 d h e 1234567891011121314 44 43424140393837363534333231 1516 3029 1718 1920 272625 c l a 1 a 2 e 44-pin tsop 2 0?5 21 24 22 23 e a b 44-pin soj 400 mils min(mils) max(mils) a 0.128 0.148 a1 0.025 - a2 1.105 1.115 b 0.026 0.032 b 0.015 0.020 c 0.007 0.013 d 1.120 1.130 e 0.370 nom e1 0.395 0.405 e2 0.435 0.445 e 0.050 nom seating plane 44-pin soj 28 pin 1 d e e2 e1 a1 b b a a2 e2 c
? as7c4098 as7c34098 5/23/02; v.1.8 alliance semiconductor p. 11 of 12 minimum ty p i c a l maximum a ?0.75? b 6.90 7.00 7.10 b1 ?3.75? c 10.90 11.00 11.10 c1 ?5.25? d 0.30 0.35 0.40 e ? ? 1.20 e1 ?0.68? e2 0.22 0.25 0.27 y ? ? 0.08 notes 1. bump counts: 48 (8 row 6 column). 2. pitch: (x,y) = 0.75 mm 0.75 mm (typ). 3. units: millimeters. 4. all tolerance are 0.050 unless otherwise specified. 5. typ: typical. 6. y is coplanarity: 0.08 (max). 48-ball fbga ball #a1 to p vi ew ball #a1 index bottom view 1 2 3 4 5 6 a c d e f g h b a a b1 c1 sram die c elastomer b side view detail view e e2 e1 d die a e e2 0.3/typ y die
as7c4098 as7c34098 ? copyright alliance semiconductor corporati on. all rights reserved. our three-point l ogo, our name and inte lliwatt are tradema rks or registered trademarks of alliance. a ll other brand and product names may be the trade- marks of their respective companies. alliance reserves the right to make changes to this documen t and its products at any time without notice. alliance assumes no responsibility fo r any errors that may appear in this document. the data contained herein represents alliance?s best data and/ or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, w ithout notice. if the product described herein is under development, significant changes to these specifications are possi ble. the information in this product data sheet is intended t o be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or cu stomer. alliance does not assume any responsibility or liability ar ising out of the application or use of any product described here in, and disclaims any express or implied warranties related to the sale a nd/or use of alliance products including liab ility or warranties rela ted to fitness for a particular purpose, merchantab ility, or infringement of any inte llectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available from alliance). all sales of alliance product s are made exclusively accordin g to alliance?s terms and condi tions of sale. the purchase of products from alliance does not convey a license under any patent ri ghts, copyrights, mask works rights, trademarks, or any oth er intellectual property rights of alliance or third parties. alli ance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasona bly be expected to result i n significant injury to the user, and the inclusion of alliance products in such life-supporting sys- tems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising fro m such use. 5/23/02; v.1.8 alliance semiconductor p. 12 of 12 ? ordering codes package ve r s i o n 10 ns 12 ns 15 ns 20 ns soj 5v commercial na as7c4098-12jc as7c4098-15jc as7c4098-20jc 5v industrial na as7c4098-12ji as7c4098-15ji as7c4098-20ji 3.3v commercial as7c34098-10jc as7c34098-12jc as7c34098-15jc as7c34098-20jc 3.3v industrial na as7c34098-12ji as7c34098-15ji as7c34098-20ji tsop 2 5v commercial na as7c4098-12tc as7c4098-15tc as7c4098-20tc 5v industrial na as7c4098-12ti as7c4098-15ti as7c4098-20ti 3.3v commercial as7c34098-10tc as7c34098-12tc as7c34098-15tc as7c34098-20tc 3.3v industrial na as7c34098-12ti as7c34098-15ti as7c34098-20ti bga 5v commercial na as7c4098-12bc as7c4098-15bc as7c4098-20bc 5v industrial na as7c4098-12bi as7c4098-15bi as7c4098-20bi 3.3v commercial as7c34098-10bc as7c34098-12bc as7c34098-15bc as7c34098-20bc 3.3v industrial na as7c34098-12bi as7c34098-15bi as7c34098-20bi bga ball arrange- ment ve r s i o n 2 5v commercial na as7c4098-12b2c as7c4098-15b2c as7c4098-20b2c 5v industrial na as7c4098-12b2i as7c4098-15b2i as7c4098-20b2i 3.3v commercial as7c34098-10b2c as7c34098-12b2c as7c34098-15b2c as7c34098-20b2c 3.3v industrial na AS7C34098-12B2I as7c34098-15b2i as7c34098-20b2i part numbering system as7c x 4098 ?xx j, t, or b x sram prefix vo l t ag e : blank: 5v cmos 3: 3.3v cmos device number access time packages: j: soj 400 mil t: tsop 2 b: 48-ball fbga 7x11 mm temperature ranges: c: commercial, 0c to 70c i: industrial, ?40c to 85c

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